AppliedMicro to License Vitesse’s 40G and 100G eFEC Cores for FPGA and ASSP Implementation in Emerging OTN Applications
CAMARILLO, Calif.--(BUSINESS WIRE)--Vitesse Semiconductor Corporation (NASDAQ: VTSS), a leading provider of advanced IC solutions for Carrier and Enterprise networks, and Applied Micro Circuits Corp., or AppliedMicro (NASDAQ: AMCC), today announced they are working together to drive a standard approach for 40G and 100G Enhanced Forward Error Correction (eFEC) technology.
“We are pleased to work with Vitesse to drive a standard eFEC approach for 40G and 100G data rates”
Forward Error Correction is widely used in fiber optic communications to reduce bit error rate in typically noisy signal environments. As metro and long-haul networks transition from 10G to 40G, and up to 100G high speed data rates, the challenges in developing cost-effective, improved signal-to-noise ratio solutions become more substantial.
“Providing the industry a standardized eFEC approach for emerging OTN solutions in metro and long-haul networks is our ultimate goal,” said Steve Perna, vice president of product marketing at Vitesse. “This effort provides significant technology advancements and value to customers who need an effective and reliable way to transmit data, voice, and video at faster rates in OTN applications. As networks migrate and Ethernet becomes the ubiquitous protocol, this capability will be increasingly critical.”
The collaboration allows AppliedMicro to license Vitesse’s patented portfolio of 40G and 100G hard decision eFEC cores for its FPGA and ASSP solutions aimed at emerging Optical Transport Network (OTN) applications requiring best-in-class net electrical coding gain (NECG) with the lowest implementation complexity and cost. The two companies will mutually cross license three OTN applications including AppliedMicro’s 10GE LAN Signal Mapping to OTU2 Signal patent and Vitesse’s Continuously Interleaved Error Correction patent.
“We are pleased to work with Vitesse to drive a standard eFEC approach for 40G and 100G data rates,” said George Jones, vice president of marketing and business development at AppliedMicro. “The combination of AppliedMicro and Vitesse supporting this family of eFEC cores in the marketplace addresses the challenges of time-to-market and interoperability. AppliedMicro’s roadmap of SoftSilicon® solutions enables immediate implementation of these eFEC cores for customer designs. Our complementary ASSP solutions will utilize the same cores and provide both software and hardware investment protection for our customers.”
Vitesse’s 40G/100G eFEC Cores
The Vitesse 40G/100G eFEC core portfolio is based on Vitesse’s patented and industry-leading Continuously Interleaved BCH (CI-BCH™) eFEC technology. CI-BCH represents a breakthrough in block coding forward error correction technology necessary for optimal signal-to-noise ratio at these high data rates. Major advantages of the CI-BCH eFEC code include: ability to optionally configure to tradeoff coding gain for reduced eFEC decoder latency in sensitive applications and the ability to occupy the lowest device resources of any eFEC code in the marketplace. The 100G 7% and 20% overhead ratio cores occupy only 31% and 54% of available Lookup Table (LUT) resources in a Xilinx Virtex 6 FPGA, respectively, meaning that 100G OTN Muxponder and Transponder solutions can be created in a single FPGA.
The 7% and 20% coding overhead versions provide 9.35dB and up to 10.5dB NECG, respectively. More specifically, at 100G operation and 7% overhead ratio, the Vitesse CI-BCH-3™ three error correcting eFEC core delivers 9.35dB NECG at an output bit error rate of 1x10E-15 and <10us decoder latency. This is better performance than any existing 7% overhead G.975.1 FEC cores on the market. For 100G operation and 20% overhead ratio, the Vitesse CI-BCH-4™ four error correcting eFEC core delivers up to 10.5dB NECG at an output bit error rate of 1x10E-15 and <10us decoder latency.
AppliedMicro Overview
AppliedMicro is a global leader in energy conscious computing solutions for telco, enterprise, data center, consumer and SMB applications. With a 30-year heritage as an innovator in high-speed connectivity and high performance embedded processing, AppliedMicro employs patented transport and embedded processor SoCs to provide high performance energy efficient products. AppliedMicro’s corporate headquarters are located in Sunnyvale, California. Sales and engineering offices are located throughout the world. For further information regarding AppliedMicro, visit the company’s Web site at http://www.apm.com.
About Vitesse
Vitesse designs, develops and markets a diverse portfolio of high-performance, cost-competitive semiconductor solutions for Carrier and Enterprise networks worldwide. Engineering excellence and dedicated customer service distinguish Vitesse as an industry leader in high-performance Ethernet LAN, WAN, and RAN, Ethernet-over-SONET/SDH, Optical Transport (OTN), and best-in-class Signal Integrity and Physical Layer products for Ethernet, Fibre Channel, Serial Attached SCSI, InfiniBand®, Video, and PCI Express applications. Additional company and product information is available at www.vitesse.com.
Vitesse is a registered trademark and CI-BCH is a trademark in the United States and/or other jurisdictions of Vitesse Semiconductor Corporation. Applied Micro Circuits Corporation, AppliedMicro and SoftSilicon are trademarks or registered trademarks of Applied Micro Circuits Corporation or its wholly owned subsidiaries. All other trademarks or registered trademarks mentioned herein are the property of their respective holders.
